1. Field of the Invention
This invention relates generally to data processing systems and more particularly to the exchange of logic signals between data processing subsystems on a system bus in the data processing system.
2. Description of the Art
Referring to FIG. 1, a typical data processing system is shown. The illustrated data processing system includes central processing units 10 and 11, input/output units 13 and 14, a main memory unit 15 and a system bus 19 coupling together the central processing, input/output and main memory units of the data processing system. The central processing unit 10 or 11 processes groups of logic signals according to software and/or firmware instructions. The logic signal groups to be processed as well as the current program in execution are typically stored in the main memory unit 15.
A console unit 12 can be coupled to the central processing units and includes apparatus and stored instructions to initialize the system. The consolel nit 12 can also act as a terminal during the operation of the data processing system. The input/output units 13 and 14 provide a user interface between the data processing system and components such as terminal units, mass storage units, comunication units, and any other units to be coupled to the data processing system.
However, a problem can arise when access to the system bus is awarded to a first unit and the appropriate activity for the implementation of the signal exchange is initiated, but the signal exchange does not result in successful processing by the receiving unit. Such a situation occurs when, for example, the main memory unit is busy and the signals applied thereto can not be processed by the main memory unit. The main memory unit can return a signal that indicates that the logic signals were or were not processed by the main memory unit through a Confirmation Acknowledge signal or a Confirmation Busy signal.
By the time that the first unit is able to retry the access to the main memory unit, the arbitration unit can have given access to other subsystems, and these other subsystems can have initiated memory activity which causes the first sub system to receive a memory busy signal again upon rearbitration by the first subsystem. Thus a situation occurs wherein a sub system of lower priority prevents a subsystem having a higher priority from gaining access to a data processing system resource, such as a main memory unit.
A possible solution to an inability of a subsystem to acquire access to a memory unit after bus access is granted in a first arbitration is to delay additional arbitration of the access to the system bus until after the exchange of the signals has taken place. In this solution, the next sequential arbitration is delayed a predetermined period to insure that the processing of the transferred signals has taken place or that unit which was awarded bus access in the first arbitration has been able to renew the request for access to the bus. This solution results in unacceptable delays in the exchange of signal groups between units.
A need has therefore been felt for apparatus and method for interaction between data processing units and a system bus such that access is granted to the system bus based on the priority of the unit requesting access while preventing inadvertent monopolization of the system bus by an inappropriate data processing system.